A practical implementation for a PCIe Gen2/Gen3 1:2 Analog MUX

Article excerpt

Mirosław Folejewski has created a practical, fully tested implementation of a 1:2 PCIe Gen2/Gen3 analog multiplexer circuit. It is designed for high-speed embedded systems and carrier boards that require switching a single PCIe lane between two independent endpoints while maintaining signal integrity at 5 GT/s (Gen2) or 8 GT/s (Gen3). The high-speed differential signals (TX/RX/REFCLK) are multiplexed using the Texas Instruments HD3SS3412, a 4-channel differential switch supporting data rates up to 12 Gbps. Auxiliary control signals (PERST#, WAKE#, CLKREQ#) are handled by SN74LVC1G3157 analog switches. You can see the files on GitHub. They are under the CERN Open Hardware Licence Version 2, Strongly Reciprocal (CERN-OHL-S-2.0).